1. Field of the Invention
The present invention generally relates to field effect transistor circuits. More specifically, the present invention relates to field effect transistors subject to bias temperature instability caused threshold voltage shifts.
2. Description of the Related Art
Modern electronic systems, for examples, computer processors, personal digital assistants (PDAs), digital cameras, currently rely on logic and storage circuits utilizing field effect transistors (FETs) fabricated on semiconductor chips. Complementary Metal Oxide Semiconductor (CMOS) circuits are widely used in such logic and storage circuitry because of the speed and relatively low power offered by CMOS circuits. CMOS circuits utilize P-channel field effect transistors (PFETs) and N-channel field effect transistors (NFETs).
Recent advances in technology have reduced the physical sizes of the FETs. Voltage supplies have been reduced to save power as well as to accommodate requirements of the reduction in the physical sizes of the FETs. FET threshold voltages (VTs) have been reduced to mitigate the performance degradation effects of reduced FET gate voltages resultant from reduction of supply voltages. As a result of the shrinking sizes of the FETs and the reduction in VTs, Negative Bias Temperature Instability (NBTI) caused VT shifts in PFETs are becoming a significant problem that results in performance degradation, voltage sensitivity, and causing what might have been marginal but operative memory storage locations to become failing storage locations. The NBTI caused VT shift causes an increase (absolute value) of VT, in a PFET, that is a function of the gate voltage relative to the source and drain voltages on the PFET. NBTI caused VT shift accumulates over time during which the PFET is in a voltage condition that stresses NBTI caused VT shift. NBTI caused VT shift in PFETs is a significant problem in today's technology. NBTI caused VT shift in PFETs is herein discussed in detail. A similar VT shift in NFETs exists, although to a lesser degree than in PFETs in current technology. Such VT shift in an NFET is called PBTI (Positive Bias Temperature Instability). The examples described hereinafter illustrate how embodiments of the present invention overcomes many of the adverse effects of NBTI caused VT shifts in PFETs; however, similar embodiments are contemplated to reduce PBTI caused VT shifts in NFETs.
A PFET is in an NBTI voltage stress condition when the source and the drain of the PFET are both at a “high” voltage level and the gate is at a “low” voltage level. For example, in a current CMOS chip having a 1-volt supply voltage, a PFET is in an NBTI voltage stress condition when its source and its drain are at 1-volt and its gate is at ground (0-volts). When the gate is “high” and the source is “high”, the PFET tends to recover somewhat from NBTI caused VT degradation. Ideally, a balanced duty cycle for PFETs (50% in an NBTI voltage stress condition, 50% not in an NBTI voltage stress condition) would produce the most uniform stress. An NFET is in a PBTI voltage stress condition when a gate on the NFET is “high” and a source and a drain of the NFET are at a “low” voltage.
Although NBTI caused VT shift is known within the industry, most methods for attempting to address the degradation problem associated with the VT shift deal with process techniques to minimize the amount of NBTI caused VT shift that occurs. However, thinning gate oxides (or other dielectric material used for the gate dielectric) and decreasing supply voltages has made the NBTI caused VT shifts that occur more significant as an overall percentage of the normal VT variability. A typical NBTI caused VT shift is 30 to 40 mV (millivolts) for a 50% duty cycle (that is, the PFET spends half of the time in an NBTI voltage stress condition, half of its time not in an NBTI voltage stress condition) of the PFET, however the NBTI caused VT shift may be 80 to 90 mV if the duty cycle is close to 100% (i.e., the PFET is almost always in an NBTI voltage stress condition). If an almost 0% duty cycle exists (i.e., the PFET is almost never in an NBTI voltage stress condition), virtually no NBTI caused VT shift occurs. Years ago, supply voltage was typically 5-volts and VT was approximately 700 mV. Currently, supply voltage is approximately 1-volt and VT is approximately 200 mV, and an NBTI caused VT shift of 80 to 90 mV is a significant percentage of the total VT of modern PFETs.
A number of use situations can cause the duty cycle of a particular PFET to be significantly other than 50%. For example, in a memory array (e.g., a static random access memory (SRAM), or dynamic random access memory (DRAM)), ABIST (array built in self test) is commonly applied during testing of the chip. ABIST is further used during burn-in stress conditions (elevated temperature and/or supply voltage) which are required to identify defects in the chip. The increased temperature and supply voltage conditions applied during burn-in increases the rate of degradation due to NBTI caused VT shifts. During burn-in, ABIST produces patterns that are coupled to the memory array. ABIST checks resultant output patterns against results expected from a memory array having no defect. The intent of these patterns is to stress the memory array, looking for all possible defect types with various disturb patterns. These patterns are needed but do not guarantee a 50% duty cycle on each bit line, word line, or storage element in the array. In fact, many sets of ABIST patterns result in a duty cycle near 100% for at least some PFETs in the memory array. Many electronic systems also run ABIST during restarts of the electronic systems. Restarts occur when the electronic system is powered up. Restarts on many electronic systems can be caused by manual intervention.
During normal operation of the electronic system, some storage elements may be written into and seldom if ever change, causing some of the PFETs to remain almost constantly in a voltage condition that causes NBTI VT shifts to accumulate. For example, operating system code is copied from nonvolatile storage such as a disk into an on-chip storage element, such as a memory array, in an electronic system such as a computer, and is normally never changed for the entire time the computer is operating. Furthermore, it is likely that the operating system code is stored into the same locations in the storage element each time the computer is restarted.
Therefore, a need exists to provide method and apparatus that minimize the NBTI caused VT shift of storage elements on semiconductor chips.